1. Field of the Invention
The technology described herein relates to a semiconductor device and its manufacturing method, and in particular, to a semiconductor device which includes a high voltage transistor and its manufacturing method.
2. Description of the Related Art
Semiconductor devices to which a high voltage is applied, such as nonvolatile memories, logic circuits mixed with nonvolatile memories and drive circuits in output stages for liquid crystal driver ICs require a high withstand voltage and a low on-resistance. Therefore, transistor elements provided in such semiconductor devices also require a high withstand voltage, and so far, various types of high voltage transistors have been developed. In particular, high voltage transistors require a long gate length for securing a withstand voltage against punch through and a low concentration impurity diffusion areas as a drift (electrical field buffering) area, and thus, the size naturally becomes much greater than that of low voltage transistors. Various technologies for reducing the scale of high withstand voltage transistor devices have been proposed and exist as the prior art (see for example Japanese Unexamined Patent Publication No. H2 (1990)-15476 (hereinafter referred to as well-known Document 1)).
FIG. 6 is a schematic cross sectional diagram showing the structure of the high voltage transistor element disclosed in well-known Document 1. In accordance with the manufacturing steps for this high voltage transistor element, first an element isolation insulating film 106 is formed in a predetermined area on an N-type semiconductor substrate 101, and a trench 109 having a predetermined length and depth is created. Next, a gate oxide film 107 and a gate electrode 105 are grown along the inner wall of the trench 109 and etched so as to have predetermined gate dimensions, and after that, a source diffusion area 102 and a drain diffusion area 103 are formed through ion implantation of a P-type high concentration impurity, and furthermore, an electrical field buffering area (pinch resistance layer) 104 is formed on the inner wall of the trench 109 on the drain 103 side through ion implantation of a P-type low concentration impurity. The electrical field buffering area 104 is formed along the inner wall of the trench 109 on the drain diffusion area 103 side.
By providing the configuration shown in FIG. 6, the gate electrode 105 and the electrical field buffering area 104 can be formed on the left and right side walls, respectively, of the trench 109 in the semiconductor substrate 1. As a result, both the length of the source diffusion area 102 and that of the drain diffusion area 104 can be reduced, and thus, the scale of the semiconductor device can be prevented from increasing as a whole, to a certain degree.
In the case of the method described in well-known Document 1, however, it is necessary to process the gate electrode 105 in such a state that the gate electrode has a step, and therefore, high-precision processing is difficult, and there is a possibility that the yield may become lower. In addition, it is also extremely difficult to make a contact connection to the gate electrode 105 having a step, and therefore, the process cannot be said to be realistic.
Furthermore, in the structure in FIG. 6, the channel area is formed in a location lower than the element isolation insulating film 106 on the semiconductor substrate 101, and therefore, the electrical field buffering effects at the ends of the channel area become very small, and thus, the possibility of the withstand voltage lowering and a leak pass being created becomes extremely high.